Optimizing Additive Formulation for Void-Free Filling in Through-Hole Plating

1. Technical Challenges & Void Formation Mechanisms

In HDI PCB and IC substrate manufacturing, void-free plating of micro-vias (e.g., 50μm diameter, 10:1 aspect ratio) faces critical challenges:

• Mass transfer limitation: Poor electrolyte flow in deep vias;

• Non-uniform current distribution: "Dog-bone" effect at via openings;

• Additive degradation: Imbalance in accelerator/inhibitor concentrations.

2. Additive System Mechanisms & Synergy

Three additive classes enable "bottom-up" filling:

2.1 Accelerators

• Function: Adsorb at via bottoms to enhance Cu²⁺ reduction;

• Example: SPS (bis-3-sulfopropyl disulfide), 1–5 ppm;

• Mechanism:

  

2.2 Suppressors

• Function: Form polymeric films at via openings to suppress over-plating;

• Example: PEG (MW 6000–8000) + Cl⁻, 50–200 ppm;

• Mechanism:

  

2.3 Levelers

• Function: Selective adsorption on protrusions to planarize deposits;

• Example: Janus Green B, 0.5–2 ppm;

• Mechanism:

  

3. Additive Ratio Optimization Strategies

3.1 DOE Methodology

Box-Behnken design with three factors (accelerator A, suppressor B, leveler C):

Responses:

• Filling Ratio (FR) = (Cu volume / Via volume) ×100%;

• Surface roughness (Ra≤0.2μm);

• Deposition rate (15–25 μm/min).

3.2 Optimization Results

Regression model (R²>0.95):

Optimal ratio: A=3.8 ppm, B=90 ppm, C=1.5 ppm, predicted FR=98.5%.

3.3 Dynamic Control

• In-line monitoring: HPLC + CVS for real-time additive tracking;

• Auto-dosing: PID-controlled pumps maintain ±5% concentration stability.

4. Process Parameter Synergy

5. Validation & Performance

• Quality tests:

  • Cross-section SEM: Void/crack inspection;

  • X-ray tomography: 3D fill ratio (±1%);

  • Thermal cycling: <2% resistance drift after 1000 cycles (-55–125°C).

• Production data:

  • Void rate reduced from 3.2% to 0.05%;

  • Plating time shortened by 30%, Cu consumption down 15%.